Scaling the 1 Transistor/1 Capacitor (1T/1C) DRAM bitcell below 40 nm presents serious challenges for several reasons. First, the DRAM capacitor requires new electrode and dielectric materials to achieve the targeted cell capacitance. While this has been relatively straightforward down to around the 40nm node, it becomes very complex and expensive between 40 and 32 nm, and there are no known solutions at 30 nm and below. Second, the aspect ratio of the capacitor structure is so large below 40 nm that etching its structures and contacting the silicon in periphery circuits becomes very complex. It is therefore expected that below 30 nm, the classic 1T/1C DRAM cell structure will be replaced by some other technology as no capacitor materials exist to provide the needed capacitance at those dimensions. In a standard DRAM bitcell, the capacitor stores the logic state, 1 or 0, and the transistor controls the access to the capacitor. To read a DRAM memory cell, the transistor is turned on and the charge on the capacitor is allowed to flow onto a bitline, creating a small voltage which can then be detected.

Because of the small geometries involved in DRAM fabrication, the capacitor can hold only a minimal charge and the resulting voltages that must be sensed are also very small. This makes the design of the circuits surrounding the memory cell difficult to design and sensitive to noise and voltage fluctuations

A Z-RAM bitcell combines the state storage of the capacitor and the access function of the transistor together into a single transistor. The logic state is stored in the floating body of the Z-RAM transistor by generating an excess of holes and a residual positive charge. An excess or an absence of holes defines the logic state, respectively a 1 or a 0. When the Z-RAM device is read, a current flows onto the bitline, allowing the state to be sensed very rapidly.

The Z-RAM technology exploits the floating body region of transistors to store a charge. This region is electrically isolated from the bulk silicon substrate by various means. In DRAM devices and possibly future logic devices, the three-dimensional (3D) transistors preferred by the major DRAM manufacturers, the device junction isolates the body region. – enabling the Z-RAM technology to be implemented on bulk substrates without requiring silicon-on-insulator (SOI) substrates. In the case of planar transistors, the isolation is obtained by using Silicon on Insulator (SOI) wafers or by well isolation.

The Z-RAM memory is a floating body memory. Initial floating body memories used relatively high voltage (2 to 2.5V) to write and read the bitcell. The Z-RAM bitcell can operate at voltages below 1V, making it the industry's lowest voltage floating body memory and the first to be on-par with DRAM voltages. Operating at low voltage is mandatory to comply with the DDR3 DRAM performance specifications and to guarantee memory reliability.

Many technologies have sought to displace DRAM as the industry's low-cost RAM solution, yet they have failed because they cannot credibly replace DRAM. Some required exotic new materials that were incompatible with semiconductor wafer fabs. Some didn't have the speed to meet DDR3 specifications, or consumed far too much power to be attractive. Some didn't have the endurance to meet DRAM cycling requirements. Only the Z-RAM technology has the combination of low-cost, high-performance, and manufacturability to be the preferred next-generation DRAM replacement.